IBM unveils sub-1nm nanostack chip concept promising massive density and efficiency gains

IBM has introduced the nanostack transistor architecture, claimed as the world’s first sub-1-nm node, which stacks transistors to fit about 100 billion onto a chip the size of a fingernail and targets a 0.7-nm/7Å node. The approach could yield roughly 50% higher performance or 70% better energy efficiency versus the 2-nm generation, with SRAM scaling improved about 40% through a staggered-channel design. The technology is developmental, not a commercial product, and IBM plans partnerships (e.g., Rapidus, Samsung) for mass production, with chips potentially entering production in 5–10 years. The “sub-1nm” label reflects performance goals rather than physical feature sizes, and IBM’s nanosheet lineage remains foundational for future transistor scaling.