All articles tagged with #nanostack
IBM unveiled the world’s first sub-1-nanometer semiconductor chip, using a nanostack architecture to vertically stack transistors and fit nearly 100 billion transistors on a fingernail-sized wafer, with up to 70% energy efficiency gains over its 2nm predecessor. Production isn’t imminent, as IBM aims to enter markets within five years and continues work on thermal management and integration challenges.
IBM announced a sub-1‑nanometer NanoStack transistor architecture that stacks nanosheets in a 3D structure to fit almost 100 billion transistors on a fingernail‑size die at a 0.7 nm class, aiming for up to 50% higher performance or 70% lower power versus its 2 nm node and a 40% SRAM density boost. The platform is designed for AI and data-center workloads and relies on advanced lithography and materials (High-NA EUV, new dielectrics), with IBM targeting a production path at sub‑1 nm within about five years through partnerships like Rapidus. While presented as a generational leap, it remains a research milestone rather than immediate mass production.
IBM announces the world’s first sub-1 nanometer chip at 0.7 nm built with a 3D nanostack transistor design, packing about 100 billion transistors in a fingernail-sized die and delivering up to 50% more performance or 70% greater energy efficiency than its 2 nm predecessor. The nanostack stacks transistors in 3D layers with material flexibility, shows 40% SRAM scaling, and points to production within five years, backed by partners and the launch of Anderon quantum-foundry; the work leverages High-NA EUV lithography and aims to push Angstrom-scale computing forward.
IBM has introduced the nanostack transistor architecture, claimed as the world’s first sub-1-nm node, which stacks transistors to fit about 100 billion onto a chip the size of a fingernail and targets a 0.7-nm/7Å node. The approach could yield roughly 50% higher performance or 70% better energy efficiency versus the 2-nm generation, with SRAM scaling improved about 40% through a staggered-channel design. The technology is developmental, not a commercial product, and IBM plans partnerships (e.g., Rapidus, Samsung) for mass production, with chips potentially entering production in 5–10 years. The “sub-1nm” label reflects performance goals rather than physical feature sizes, and IBM’s nanosheet lineage remains foundational for future transistor scaling.