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Nanostack

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technology3 hours ago•5 min saved

IBM Unveils 0.7 nm Nanostack Chip, Pushing Angstrom-Scale Computing

IBM announces the world’s first sub-1 nanometer chip at 0.7 nm built with a 3D nanostack transistor design, packing about 100 billion transistors in a fingernail-sized die and delivering up to 50% more performance or 70% greater energy efficiency than its 2 nm predecessor. The nanostack stacks transistors in 3D layers with material flexibility, shows 40% SRAM scaling, and points to production within five years, backed by partners and the launch of Anderon quantum-foundry; the work leverages High-NA EUV lithography and aims to push Angstrom-scale computing forward.

via IBM Newsroom|

#3d-architecture #ibm #nanostack

technology3 hours ago•5 min saved

IBM unveils sub-1nm nanostack chip concept promising massive density and efficiency gains

IBM has introduced the nanostack transistor architecture, claimed as the world’s first sub-1-nm node, which stacks transistors to fit about 100 billion onto a chip the size of a fingernail and targets a 0.7-nm/7Å node. The approach could yield roughly 50% higher performance or 70% better energy efficiency versus the 2-nm generation, with SRAM scaling improved about 40% through a staggered-channel design. The technology is developmental, not a commercial product, and IBM plans partnerships (e.g., Rapidus, Samsung) for mass production, with chips potentially entering production in 5–10 years. The “sub-1nm” label reflects performance goals rather than physical feature sizes, and IBM’s nanosheet lineage remains foundational for future transistor scaling.

via Ars Technica|

#ai #ibm #nanostack