IBM's 0.7nm NanoStack: nearly 100 billion transistors on a fingernail chip

IBM announced a sub-1‑nanometer NanoStack transistor architecture that stacks nanosheets in a 3D structure to fit almost 100 billion transistors on a fingernail‑size die at a 0.7 nm class, aiming for up to 50% higher performance or 70% lower power versus its 2 nm node and a 40% SRAM density boost. The platform is designed for AI and data-center workloads and relies on advanced lithography and materials (High-NA EUV, new dielectrics), with IBM targeting a production path at sub‑1 nm within about five years through partnerships like Rapidus. While presented as a generational leap, it remains a research milestone rather than immediate mass production.