Vertical silicon stack unlocks denser, cooler chips
A University of Illinois team demonstrated monolithic 3D integration by stacking ultrathin silicon nanomembranes (about 10 nm thick) on top of existing circuits at temperatures below 200°C, achieving 98–100% device yields across three stacked layers of 625 transistors each. Using junctionless transistors and dense vertical interconnects, they built multi-layer logic and SRAM with strong performance and low thermal budget, showing a scalable path toward commercial 3D silicon chips that could extend Moore’s Law. The work, published in Nature, is positioned for industrial transfer with partners including IBM, Intel, and TSMC.