Moore’s Law Goes Vertical: Stacked Silicon Chips Boost Compute Density
University of Illinois researchers demonstrate monolithic 3D silicon by stacking ultrathin silicon membranes to build a three-layer stack with 625 transistors per layer and high yields (98–100%), using low-temperature transfer and junctionless devices to stay within a ~400 C thermal budget. The approach, enabled by roll-laminated ~10 nm membranes, promises tighter interlayer connections and faster 3D SRAM/logic, with a clear path toward industrial manufacturing for commercial foundries like IBM, Intel, and TSMC.