All articles tagged with #logicfolding
Huawei unveiled a new 'LogicFolding' approach to manufacture its Kirin smartphone chips this fall, aiming for 1.4-nm‑class capabilities by 2031 despite U.S. sanctions. The move comes as Nvidia faces export restrictions in China and Apple remains a key competitor, though experts caution that the method’s real-world scalability, heat management, and yields remain unproven at scale.
At the 2026 IEEE ISCAS, Huawei’s He Tingbo introduced the Tau (τ) Scaling Law, a time-based alternative to traditional geometric scaling for semiconductors and electronic systems. The approach uses LogicFolding and a multi-level, software–hardware co-design to shorten the signal time constant and boost transistor density, circuit performance, and energy efficiency across devices, circuits, chips, and systems. Huawei says it has designed 381 τ-based chips, with Kirin models slated to adopt LogicFolding in Fall 2026, and envisions future high-end chips reaching ~14 Å density by 2031, while calling for open collaboration across the industry.
Huawei says it has a new pathway, dubbed LogicFolding, to shrink its gap with leader TSMC by aiming to mass-produce 1.4‑nanometer chips by 2031, a move that could challenge the need for ASML’s advanced EUV equipment since TSMC has said it will mass-produce 1.4nm by 2028. If Huawei can scale this, it would mark a significant step in China’s push for semiconductor self-sufficiency and shorten the industry lead held by TSMC, though the plan hinges on large‑scale manufacturing capabilities and technological breakthroughs.