Huawei Unveils Tau Scaling Law to Accelerate Transistors and System Performance
At the 2026 IEEE ISCAS, Huawei’s He Tingbo introduced the Tau (τ) Scaling Law, a time-based alternative to traditional geometric scaling for semiconductors and electronic systems. The approach uses LogicFolding and a multi-level, software–hardware co-design to shorten the signal time constant and boost transistor density, circuit performance, and energy efficiency across devices, circuits, chips, and systems. Huawei says it has designed 381 τ-based chips, with Kirin models slated to adopt LogicFolding in Fall 2026, and envisions future high-end chips reaching ~14 Å density by 2031, while calling for open collaboration across the industry.
