Tag

Vertical Stacking

All articles tagged with #vertical stacking

technology23 days ago•5 min saved

Moore’s Law Goes Vertical: Stacked Silicon Chips Boost Compute Density

University of Illinois researchers demonstrate monolithic 3D silicon by stacking ultrathin silicon membranes to build a three-layer stack with 625 transistors per layer and high yields (98–100%), using low-temperature transfer and junctionless devices to stay within a ~400 C thermal budget. The approach, enabled by roll-laminated ~10 nm membranes, promises tighter interlayer connections and faster 3D SRAM/logic, with a clear path toward industrial manufacturing for commercial foundries like IBM, Intel, and TSMC.

via TechSpot|

#junctionless-transistors #monolithic-3d-integration #semiconductor-manufacturing

technology24 days ago•6 min saved

Vertical silicon stack unlocks denser, cooler chips

A University of Illinois team demonstrated monolithic 3D integration by stacking ultrathin silicon nanomembranes (about 10 nm thick) on top of existing circuits at temperatures below 200°C, achieving 98–100% device yields across three stacked layers of 625 transistors each. Using junctionless transistors and dense vertical interconnects, they built multi-layer logic and SRAM with strong performance and low thermal budget, showing a scalable path toward commercial 3D silicon chips that could extend Moore’s Law. The work, published in Nature, is positioned for industrial transfer with partners including IBM, Intel, and TSMC.

via ScienceDaily|

#monolithic-3d-integration #moores-law #semiconductor-manufacturing