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Epyc Venice

All articles tagged with #epyc venice

technology1 month ago•6 min saved

Intel’s Diamond Rapids Xeon 7 Eyes on AI with 256 P-Cores and Gen6 I/O

Intel previewed Diamond Rapids Xeon 7 data‑center CPUs on the 18A‑P process with up to 256 P‑Cores, a shared 1.28 GB L3/LLC, 16‑channel DDR5 memory up to 12,800 MT/s, and 128 PCIe Gen6 lanes plus CXL 3.0. The chips use a disaggregated, multi‑tile SoC design with Foveros Direct 3D and UCIe‑S interconnect to boost AI workloads, and are positioned against AMD EPYC Venice. SMT is not included in this generation; Coral Rapids will reintroduce SMT later (mid‑2028 launch targeted). Launch cadence may accelerate due to AI demand.

via Wccftech|

#diamond-rapids #epyc-venice #intel

technology2 months ago•4 min saved

AMD Unveils Zen 6 Venice EPYC: 256‑Core HPC Power on 2nm

AMD teased its 6th‑gen EPYC Venice CPUs based on Zen 6, led by a 256‑core flagship built for HPC and AI workloads. The chip combines eight CCDs with two large IO dies, and uses TSMC’s 2nm process to enable PCIe 6.0, UCIe, and DDR5 support, delivering AMD’s claimed ~70% gains in performance and efficiency and a 30%+ increase in thread density. Positioned for Helios AI racks to handle agentic AI workloads, Venice faces competition from Nvidia’s Vera systems as CPUs become more central to data‑center AI workflows.

via Wccftech|

#2nm #amd #epyc-venice

technology7 months ago•8 min saved

AMD and Meta Expand AI Compute Pact to 6 GW of Instinct GPUs

AMD and Meta have broadened their multi-year partnership to deploy up to 6 gigawatts of AMD Instinct GPUs across multiple generations, beginning with a MI450-based GPU on the Helios rack-scale architecture for Meta’s AI workloads, with shipments for the first gigawatt due in the second half of 2026; the deal also deepens collaboration on 6th‑Gen EPYC CPUs codenamed Venice (and Verano) and expands a performance-based stock warrant of up to 160 million shares tied to milestones, aligning silicon, systems and software roadmaps to accelerate global AI infrastructure deployment.

via AMD|

#amd #epyc-venice #instinct